Complementary metal-oxide-semiconductor (CMOS) technology is a dominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits today. However, the fabrication of CMOS devices faces significant challenges. One of the challenges resides in the fabrication of implanted regions, such as source/drain regions, an n-well or a p-well. In order to fabricate the implanted regions using different types of ions, a sacrificial oxide layer is first deposited on a substrate, and then a resist layer is deposited and patterned on the sacrificial oxide layer to expose predetermined positions of the substrate, thereby implanting ions at the predetermined positions but not at other positions of the substrate. Then, the patterned resist layer is removed. Thereafter, the aforementioned process is repeated to form other implanted regions using other types of ions. Generally, the resist layer is patterned by using a dry etching process. However, the sacrificial oxide layer is often damaged by the dry etching process, thus causing the sacrificial oxide layer to have non-uniform thickness. Thus, due to the non-uniform thickness of the sacrificial oxide layer, and the ion are implanted in different depths of the substrate, which is detrimental to controlling the stability of ion implantation.